Altera

Altera

Senior Debug Verification Engineer

San Jose, California, United States · Senior

Sponsorship not specified$149k-$215kDetected 31 days ago
PythonLinuxFPGAVerilogCommunication

About the role

  • Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification.
  • Using system full application to verify performance and identify short falls.

Responsibilities

  • Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
  • Create testcase and testbench with UVM methodology

Requirements

  • 8+ years of experience with complex ASIC designs and/or verification
  • 8+ years of experience with SystemVerilog language
  • 8+ years of experience on UVM verification methodology, and formal verification method
  • 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
  • Strong communication skills and the ability to work with a team spread across different geography sites
  • Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
  • Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.

Nice to have

  • Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.

Skills

  • About Altera

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $149,100 - $215,000 USD

Benefits

  • Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
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This listing is sourced directly from Altera's careers page and normalized into a canonical job model.