Cspeed
PCB Design & Validation Engineer
Palo Alto, CA
Sponsorship not specifiedDetected 6 days ago
PythonData AnalysisNLPPCB DesignAltiumCadenceElectrical EngineeringTest Automation
About the role
- Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA.
Responsibilities
- Own schematic capture, component selection, and layout for test/eval boards, development platforms, and transceiver module PCBs
- Design multi-layer, controlled-impedance boards with high-speed NRZ routing, mixed-signal considerations, and PDN design
- Manage DRC, fab outputs (Gerbers, assembly drawings), vendor coordination
- maintain schematic/footprint libraries
- Develop and execute validation plans covering silicon, module, and system-level testing with defined pass/fail criteria
- Characterize SerDes performance (jitter, eye diagrams, BER, equalization) and validate data pipeline throughput across PVT corners
- Validate optical subsystems (laser/modulator power, extinction ratio, wavelength stability
- Build test setups and Python automation
- create data analysis pipelines
- Manage DRC, fab outputs (Gerbers, assembly drawings), vendor coordination; maintain schematic/footprint libraries
Requirements
- Proficiency with PCB design tools (Altium Designer, Cadence Allegro, or equivalent)
- Proficiency with lab instrumentation: real-time oscilloscopes, BERT, optical power meters, VNA, TDR
- familiarity with I2C, SPI, and serial protocols
Nice to have
- Experience with NRZ optical transceiver validation and silicon characterization across PVT corners
- Familiarity with SI/PI simulation tools (HyperLynx, HFSS, ADS)
- Experience with CMIS or similar management interfaces
- Ethernet compliance testing
- Knowledge of reliability testing methodologies (Telcordia, JEDEC) and FEC performance validation
- Experience in a startup or fast-paced development environment
This listing is sourced directly from Cspeed's careers page and normalized into a canonical job model.