Winmaxsystemscorporation
Design Verification Engineer
Menlo Park, CA, United States
Sponsorship not specifiedDetected 3445 days ago
PythonGitFPGAVerilogHardware DesignCommunication
About the role
- Develop FPGA Design Verification tests, and test plans
- Review Detailed Design specifications for logic to be tested
Requirements
- BS, MS CS, EE or related discipline, or 7+ years of equivalent experience
- Expertise in system Verilog, and UVM
- Experience with bug tracking (e.g. bugzilla), revision control (e.g. git), and build systems (e.g. make)
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