Marvell Technology

Distinguished Engineer - Digital Design

US-CA - San Diego, USA · Internship

Sponsorship not specified$12k-$15kDetected 15 days ago

PythonLinuxProject ManagementVerilogElectrical EngineeringLeadershipCommunication

About the role

Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs.

RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
Ability to create SVA assertions and apply formal verification concepts and tools
Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow
Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 17+ years of related professional experience.
Or Master's degree in Computer Science, Electrical Engineering or related fields with 12-15+ years of experience.
Or PhD in Computer Science, Electrical Engineering or related fields with 10-12+ years of experience.
Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies.
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.
As such, applicants must be eligible to access export-controlled information as defined under applicable law.
Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State.

Shape the micro-architecture of the chip
Write SVA assertions for dynamic simulation and apply them in formal verification
Interact with the project manager to scope and assign tasks
Provide reasonable and accurate schedule estimates and follow through to meet them in spite of surprises
Proactively communicate challenges and provide contingency plan recommendations to management
Work with the software team to ensure product meets customer use cases

Fluent in SystemVerilog RTL coding techniques.
Experience in high speed, multiple clock domain designs
Expertise in PCIe, CXL protocols
Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
Experience in implementation/timing closure for high speed design.
Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
Excellent verbal and written communication
Discipline and rigor in documentation
Ability to work efficiently and influentially with team members across multiple sites

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

export control laws and regulations, including the Export Administration Regulations (EAR)

This listing is sourced directly from Marvell Technology's careers page and normalized into a canonical job model.