Sifive

Senior RTL Design Engineer - CPU Frontend

Santa Clara, California, United States · Senior · Contract

Sponsorship not specified$159k-$194kDetected 26 days ago

ScalaGitMachine LearningJiraVerilogElectrical Engineering

About the role

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
With SiFive, the future of RISC-V has no limits.
Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.

BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
Test-driven development, particularly ability to write adaptive unit tests
Ability to work well with others and share the belief that engineering is teamwork.
Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.

$158,760.00-$194,040.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.

Knowledge of verification principles, testbenches, UVM, and coverage.
In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

ntingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any ne

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