Chipagents

Chipagents

Formal Verification Engineer

San Jose

Sponsorship not specifiedDetected 40 days ago
PythonLLMsAgentic AIVerilogHardware DesignResearch

About the role

  • We are seeking a highly capable Formal Verification Engineer to join our core product and research team.
  • Your expertise in formal methods, property specification, assertion-based verification, and proof debugging will help shape how AI systems reason about complex hardware behavior.

Responsibilities

  • Collaborate with AI engineers and researchers to model and codify formal verification workflows.
  • Use formal verification tools to analyze RTL designs, prove design correctness, and identify functional bugs.
  • Create reusable formal verification examples, design patterns, proof strategies, and edge cases to train and evaluate AI agents.
  • Help AI systems interpret design specifications, generate, reason about RTL behavior, and debug counterexamples.
  • Support benchmarking and evaluation of AI-assisted formal verification productivity across realistic IP and SoC verification tasks.
  • You will play a central role in teaching our AI agents how verification engineers develop, analyze counterexamples, close proof convergence gaps, and validate RTL designs with mathematical rigor.
  • This is a unique opportunity to apply deep formal verification expertise at the frontier of AI-assisted chip design.
  • In this role, you will work closely with our AI engineering, research, and EDA teams to build advanced agentic AI systems for semiconductor verification.

Requirements

  • Strong expertise in formal verification methodologies and signoff flows.
  • Hands-on experience with JasperGold, VC Formal, Questa Formal, or equivalent tools.
  • Deep knowledge of SystemVerilog Assertions (SVA) and assertion-based verification.
  • Experience proving complex, debugging counterexamples, and achieving formal closure.
  • Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.
  • Experience with CDC, RDC, lint, and static verification methodologies.
  • Experience verifying production IPs, subsystems, or SoCs.
  • Proficiency in Python, Tcl, or scripting for verification automation.
  • Strong RTL design and microarchitecture understanding.
  • Interest in applying AI/LLMs to hardware design and verification workflows
  • Work at the frontier of AI and semiconductor design.
  • Collaborate with a world-class team spanning AI, systems, and EDA.
  • Shape a foundational shift in how chips are built.

Compensation

  • We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.

Benefits

  • $150K/yr - $350K/yr + Offers Equity.
  • Unlimited PTO and full benefits (medical, vision, dental, 401k).
  • Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.
  • Develop, refine, and debug SystemVerilog Assertions, formal, assumptions, constraints, and coverage objectives.
  • Contribute to methodology development for assertion-based verification, formal apps, equivalence checking, connectivity checking, and coverage closure.

Company info

  • Work closely with customers, product, and research teams to translate formal verification pain points into automated AI workflows.
  • We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.
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