Etched
Advanced Packaging SI/PI Engineer
San Jose · Senior
Sponsorship not specifiedDetected 57 days ago
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odds of building a lasting career here
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Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70
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About the role
- As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board.
- Intense focus on pushing what is possible in power delivery and high-speed signaling for our silicon.
Responsibilities
- SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
- Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance
- Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.
- Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.
- Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.
- Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization.
- Participating in cross-functional meetings and design reviews.
- Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
- Relocation support for those moving to San Jose (Santana Row)
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.
- 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
- Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.
- Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs.
- Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization.
- Familiarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN.
- Experience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design.
- You may be a good fit if you have (Must-have qualifications)
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
Company info
- We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes.
- We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.
This listing is sourced directly from Etched's careers page and normalized into a canonical job model.