Lattice Semiconductor
Principal Engineer Synthesis Team
San Jose, CA · Principal
Sponsorship not specifiedDetected 20 days ago
PythonC++AlgorithmsCode ReviewLLMsProduct ManagementProduct StrategyCustomer SuccessCustomer SupportFPGAElectrical EngineeringManual TestingLeadership
About the role
- Lattice Overview There is energy here…energy you can feel crackling at any of our international locations.
- Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
- This role is central to delivering high-quality, scalable synthesis solutions across the Lattice product portfolio, with primary ownership of the Lattice synthesis toolchain.
Responsibilities
- Provide technical leadership in the design, implementation, and optimization of FPGA synthesis engines across multiple Lattice product families
- Collaborate with synthesis developers and cross-functional partners to define architecture, algorithms, and long-term technical direction
- Drive quality-of-results (QoR) improvements spanning Fmax, area, and compile time
- Lead development and enablement of new synthesis features and capabilities aligned with product roadmap priorities
- Maintain, enhance, and modernize the synthesis codebase to ensure robustness, scalability, and long-term maintainability
- Influence engineering best practices, code quality, and design standards within the synthesis team
- Mentor and guide junior and mid-level engineers through design reviews and technical guidance
Requirements
- 10+ years of experience in EDA software development, with a focus on logic synthesis or place-and-route
- Expert-level proficiency in C++, with a track record of designing, implementing, and optimizing large-scale, performance-critical software systems
- Deep knowledge of synthesis algorithms - including technology mapping, retiming, logic optimization, and timing-driven optimization
- Strong understanding of FPGA architectures (LUTs, DSPs, BRAMs, carry chains) and how architectural constraints inform synthesis strategy
- Experience with QoR benchmarking methodologies and data-driven optimization workflows
- Hands-on experience with generative AI tools applied to developer productivity - debugging, code review, algorithm exploration, or documentation
Nice to have
- Familiarity with the Lattice synthesis toolchain (Radiant, Propel, or ACE environments)
- Experience with Python scripting for automation, regression testing, or QoR analysis
- M.S. or Ph.D. in Computer Science, Electrical Engineering, or a related field
- Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.
- The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.
Compensation
- In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Benefits
- In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Company info
- For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.
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