Cadence
Intern - Characterization and Support
SAN JOSE · Intern · Internship
Sponsorship not specifiedDetected 15 days ago
PythonCadenceElectrical EngineeringControlsTest AutomationCommunicationCollaborationProblem Solving
About the role
- This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern.
Nice to have
- Responsible for validating both system-level and electrical performance of internal silicon test chips.
- The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.
- The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
- Very good fundamentals in analog and digital electronics, RTL, Signal integrity, control systems
- Strong analytical and problem-solving skills
- The role is open for candidates with Bachelor's or master's degree in electrical engineering with 0-2 years of relevant work experience
- Excellent written and verbal communication skills
- Ability to work collaboratively in a team environment
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