Lumilens

Design Engineer

San Jose

Sponsorship not specifiedDetected 15 days ago

PythonNode.jsFPGAVerilog

About the role

Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification.
It's a hands-on role with room to grow your scope as the team and the chip mature.

Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
Design and implement front-end RTL blocks in SystemVerilog - datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
Integrate IP and support parameterization for configurability.
Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
Power- and timing-aware design - managing block activity, clock-gating, pipelining, and retiming
partner with the backend team on physical closure for your blocks.
support DV and silicon bring-up, including DFT/debug hooks in your blocks.
Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.
3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).

Lint and CDC/RDC discipline and clean-RTL practices.
comfort with synthesis and timing closure, working with the backend team.
Strong debug skills in simulation
scripting in Python, Perl, or TCL.
FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
Assertion-based verification (SVA) and familiarity with UVM block-level testbenches
emulation / FPGA prototyping experience.
Exposure to scale-up / scale-out interconnects or network switch / NIC / memory-controller datapaths.

This listing is sourced directly from Lumilens's careers page and normalized into a canonical job model.