Samsung Semiconductor
Senior Engineer, Physical Design AI/ML
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$17,896 more — $155,896 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Green-card intent detected
Green-card follow-through: 44%
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more.
- We believe innovation and growth are driven by an inclusive culture and a diverse workforce.
Responsibilities
- Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the team
- Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the team
- Collaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systems
- The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes.
Requirements
- Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)
- The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.
- RTL synthesis, place and route, and timing analysis skills
- Understanding of clock and power delivery network schemes
- Hands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks
- Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow
- Experience in using Bayesian optimization and/or active learning frameworks for design space exploration
- You're inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Nice to have
- Familiarity with state-of-the-art AI workloads and their compute and memory requirements
- Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models
- Proficiency in EDA tools for synthesis and layout
- We also offer incentive opportunities that reward employees based on individual and company performance.
- An investment in your future is an investment in ours.
- Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
- Stay Fit Eating well and being active are important parts of a healthy life.
- PhD with industry experience preferred
Skills
- Advancing the World's Technology Together
Compensation
- $138,000 - $206,000 USD
Benefits
- This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
- In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
- Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
- Care for Family Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
- Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
- Embrace Flexibility Benefits are best when you have the space to use them.
- That's why we facilitate a flexible environment so you can find the right balance for you.
- Applying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditions
- Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D team
- Our onsite Café and gym, plus virtual classes, make it easier.
Company info
- The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose.
- Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency.
Equal opportunity
- Employment Policy
- Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
- When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication.
- We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support.
This listing is sourced directly from Samsung Semiconductor's careers page and normalized into a canonical job model.