River
Member of Technical Staff, Hardware, Design Verification Engineer
Palo Alto, CA; Austin, TX · Staff+
H1B sponsorship available$200k-$420kDetected 25 days ago
PythonBashObject-Oriented ProgrammingCI/CDDeep LearningLogisticsVerilogElectrical Engineering
About the role
- We are looking for exception design verification engineers to ensure our high-performance custom silicon is functionally correct.
- Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc).
- You will collaborate with RTL design, performance modeling and verification, and compiler teams.
Responsibilities
- UVM Environment Development: Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
- Emulation: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
- Automation & Scripting: Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.
- Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
Requirements
- Bachelor's degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
- Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
- Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
Nice to have
- (We encourage you to apply even if you don't meet all of these)
- Proficiency SystemVerilog Assertions (SVA) and formal tools ( Jasper, VC Formal) to catch temporal logic bugs at the source.
- Understanding of emulation and prototyping solutions and test environments.
- Hands-on experience in post-Silicon bringup, testing, and debug.
- Experience in workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.
- Visa Sponsorship: We sponsor visas.
- We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
Compensation
- Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
Benefits
- River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
- Constrained-Random Testing: Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
- Coverage-Driven Verification: Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
- Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
Company info
- We are scientists, engineers, and builders from the industry's top tech companies and AI labs.
- We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
- At River, our mission is to create personal AI owned and shaped by each individual.
- personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
Visa & Work Authorization
- We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
- We sponsor visas.
This listing is sourced directly from River's careers page and normalized into a canonical job model.