NXP Semiconductors
Senior Design Verification Engineer
Austin (Oakhill, Office) · Senior
Sponsorship not specifiedDetected 30 days ago
PythonC++Machine LearningVerilogProblem Solving
About the role
- Creating intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
- Defining and writing System Verilog Assertion (SVA) cover to match the verification plan.
- Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness.
Responsibilities
- Design Verification Engineer
- The design verification engineer will work with other members of the architecture, design and verification teams to verify IP designed in-house or purchased from 3 rd party vendors.
Requirements
- Minimum 4 years of experience in IP or SoC design or verification.
- Verilog, SystemVerilog, UVM coding skills required.
- Verification skills (test planning, testcase, testbench, simulation, debug) required.
- Ability to work independently and in small teams without close supervision required.
- Minimum BSEE/BSCE/BSCS. MSEE/MSCE/MSCS a plus.
- Design skills (design documentation, RTL coding, synthesis, static and formal checkers, etc.) a plus.
Nice to have
- Minimum BSEE/BSCE/BSCS.
- MSEE/MSCE/MSCS a plus.
- Other programming skills (Python, C/C++, Perl, TCL, etc.) a plus.
- Knowledge of ARM AMBA® protocols a plus.
Skills
- Hands on experience in using AI/ML tools for workflow and productivity improvements.
Equal opportunity
- More information about NXP in the United States...
- NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law.
- In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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