Altera
Senior Director, Silicon Hardware Engineering - Boards, Packaging, & Reliability
San Jose, California, United States · Director
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$5,058 more — $236,558 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $236,558 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Computer Hardware Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Computer Hardware Engineers (17-2061) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Establish clear goals, KPIs, engineering standards, and performance expectations across all teams.
- Champion rigorous signal integrity (SI) and power integrity (PI) methodologies, ensuring consistent engineering standards and adoption of best-in-class EDA tooling across teams.
Responsibilities
- Lead, develop, and scale three core engineering functions: chip package development, board hardware development, and silicon power and reliability engineering.
- Build, mentor, and develop high-performing engineering teams distributed across the U.S. and Asia, fostering a collaborative, accountable, and results-driven culture.
- Partner closely with VP/SVP leadership to define multi-year technical roadmaps, headcount plans, and organizational strategy.
- Drive technical and organizational alignment across the three functions to improve execution, quality, and predictability across product programs.
- Define and drive technical direction for advanced package technologies including 2.5D/3D IC, flip-chip, and high-density interconnect.
- Oversee board-level hardware development from concept through bring-up, ensuring design-for-manufacturability and design-for-test.
- Lead silicon power and reliability programs including power budgeting, electromigration, ESD, and reliability qualification.
- Apply deep knowledge of silicon design development methodologies to improve tapeout quality, schedule, and first-pass silicon success rates.
- Drive disciplined technical reviews and engineering decision-making across package, board, SI/PI, power, and reliability activities to identify and mitigate product risks early.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or closely related field required
- 15+ years of progressive experience in semiconductor hardware engineering, with at least 5 years in a senior leadership or director-level role.
- Demonstrated experience managing global, cross-functional engineering teams across U.S. and Asian sites.
- Strong hands-on background in signal integrity and power integrity analysis and methodologies, including experience with industry-standard tools such as Ansys SIwave, Cadence Sigrity, HyperLynx, or equivalent.
- Track record of delivering measurable cost-reduction programs across package and board hardware while maintaining product quality and technical requirements.
- Experience managing and qualifying multiple external vendors and OSATs simultaneously.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or closely related field required; Master's Degree preferred.
- Deep technical expertise in chip package development, including advanced packaging, substrate design, and OSAT management.
- Proven experience in chip board hardware development, including schematic design, PCB layout, and bring-up.
- Solid understanding of silicon design development methodologies, including synthesis, place and route (P&R), timing closure, and DFT.
- Demonstrated ability to drive complex engineering programs and technical decisions across organizational boundaries.
- Excellent communication, influencing, and executive presentation skills.
Nice to have
- Master's Degree preferred.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $231,500 - $335,000 USD
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.