Astera Labs Inc.
Senior ATE Test Engineer
San Jose, California, United States · Senior
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$24,244 more — $159,744 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $159,744 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Quality Assurance Analysts and Testers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Software Quality Assurance Analysts and Testers (15-1253) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- We are looking for Senior ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions.
- The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp.
- The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.
Responsibilities
- This is an opportunity to contribute hands-on technical expertise within Astera Labs' hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems.
Requirements
- ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.
- Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
- Professional attitude with ability to execute on multiple tasks with minimal supervision.
- Required Experience
- Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
Nice to have
- Strong academic and technical background in electrical engineering.
- At minimum, a Bachelor's in EE is required, and a Master's is preferred.
Compensation
- Salary range is $135,500 to $170,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.