Lumilens

Lumilens

Power Integrity Engineer-Silicon

San Jose

Sponsorship not specifiedDetected 34 days ago
Node.jsFull-Stack DevelopmentSupply ChainANSYSCadenceEMI/EMCElectrical EngineeringLeadershipCommunication

About the role

  • Analyze and mitigate power-related reliability risks, including electromigration, thermal-induced voltage droop, power sequencing, and long-term stability under dynamic AI workloads.
  • Proven track record leading power integrity efforts in advanced packaging environments, including 2.5D/3D integration, chiplets, silicon interposers/bridges, FOWLP, CoWoS, hybrid bonding, or similar technologies.

Responsibilities

  • Define and implement power integrity architectures for 2.5D/3D heterogeneous integration, including chiplet-based designs, interposer/substrate scaling, on-package voltage regulation, multi-rail PDN topologies, decoupling strategies, and power-aware thermal co-design.
  • Perform comprehensive full-stack power integrity analysis and optimization-from die-level IR drop and electromigration to package-level PDN impedance profiling, transient response, and system-level power delivery network (PDN) validation.
  • Model, simulate, and validate power delivery solutions using industry-leading tools (e.g., Ansys SIwave, HFSS, Cadence Sigrity, Apache RedHawk, Voltus, or equivalent) across silicon, interposer, substrate, and board interfaces.
  • Lead power integrity co-design with silicon design, package engineering, and photonics teams to optimize bump maps, power/ground grid layouts, TSV/RDL routing, on-die decoupling, and voltage regulator placement for minimal noise, IR drop, and EMI in CPO/NPO systems.
  • Drive selection and qualification of advanced power components (VRMs, capacitors, inductors, low-loss substrates, advanced TIMs) and collaborate with foundry/OSAT partners on PDN process capabilities, manufacturability, yield, and cost.
  • Develop and refine power integrity methodologies, design rules, and sign-off criteria tailored to high-performance AI accelerators, photonic transceivers, and chiplet architectures.
  • Partner with cross-functional teams (architecture, Si design, package design, system engineering, supply chain) to explore emerging technologies, influence roadmaps, generate proof-of-concepts, and protect IP that maximizes power efficiency and performance.
  • Own power integrity qualification, lab validation (using high-bandwidth scopes, VNAs, spectrum analyzers), correlation to simulation, and readiness for volume production ramp.

Requirements

  • Bachelor's degree in Electrical Engineering, Physics, or related field + 10+ years relevant industry experience
  • or Master's/PhD + 7+ years related experience.
  • Hands-on proficiency with PI simulation tools (Ansys, Cadence/Sigrity, Keysight ADS, Apache/RedHawk, or equivalents) and correlation to silicon measurements.

Nice to have

  • Experience with power integrity in silicon photonics, CPO/NPO, photonic IC/laser integration, or high-bandwidth optical interconnects for AI accelerators.
  • DTCO for 3D IC solutions
  • Prior work defining long-term PDN roadmaps and executing from concept through high-volume manufacturing in hyperscale AI or HPC environments.
  • Leadership in multi-supplier or multi-company power integrity initiatives with measurable impact on performance, efficiency, or cost.
  • Familiarity with signal integrity/power integrity co-optimization, high-speed SerDes, PCIe/CXL interfaces, HBM integration, or advanced memory subsystems.
  • Familarity with photonic and electrical IC foundry processes (BICMOS, Advanced node CMOS...etc)
  • Knowledge of board/system-level power delivery requirements and multi-physics considerations (thermal-electrical coupling).
  • Why Join Lumilens?

Skills

  • This isn't incremental innovation, it's a ground-floor opportunity to rethink the optical layer from the silicon up.

Company info

  • We're looking for a world-class Senior / Principal Power Integrity Engineer to own and drive power delivery strategies across complex 2.5D/3D packages that integrate electrical ICs, photonic ICs, chiplets, and high-bandwidth memory.
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