Altera
Product Architectural Model Development Leader
San Jose, California, United States · Senior
Sponsorship not specified$232k-$341kDetected 16 days ago
PythonC++Product ManagementFPGAVerilogElectrical EngineeringSignal ProcessingLeadershipCommunication
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odds of building a lasting career here
61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
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About the role
- These models will also enable customers earlier in the product lifecycle through pre-silicon functional simulation, early RTL and data-flow development, and software and driver development ahead of device availability.
- Champion automation to reduce hand-off latency between architecture spec, model, RTL, and verification
- Hire, mentor, and grow a team of behavioral/architecture modeling engineers
Responsibilities
- Lead a team of behavioral modeling engineers responsible for developing cycle-approximate and functional models of FPGA architecture (fabric, DSP blocks, memory hierarchies, hard IP, transceivers, NoC, etc.)
- Define modeling methodology, coding standards, and architecture for behavioral models (C++, SystemC, Python) used across the pre-silicon design flow
- Own the roadmap for model development in lockstep with architecture definition milestones - from early concept and pathfinding through RTL freeze
- Drive model accuracy, performance, and maintainability trade-offs, ensuring models scale across increasingly complex FPGA generations
- Partner with silicon architects to translate architectural specifications and microarchitecture decisions into executable behavioral models
- Establish the architectural model as a trusted internal product reference for intended system behavior, functional flows, interfaces, and architectural rules across architecture, design, verification, firmware, and software teams
- Collaborate with verification teams to ensure behavioral models serve as golden references / scoreboards for RTL verification (UVM environments, formal checking, co-simulation)
- Work with performance modeling and pathfinding teams to support design-space exploration, power/performance/area (PPA) trade-off studies, and early customer workload analysis
- Drive early customer enablement by delivering models that support pre-silicon prototyping, functional simulation, RTL and data-flow development, and evaluation of product capabilities before silicon availability
- Support software, firmware, compiler, driver, and tools teams that depend on behavioral models for early development, platform bring-up, and functional simulation ahead of silicon availability
Requirements
- 15+ years of experience in silicon architecture, design, or verification, with 5+ years in a technical leadership role
- Experience bridging architecture specifications into simulatable models used for verification and/or performance analysis
- Experience using pre-silicon models to enable software, firmware, drivers, or customer development ahead of RTL or silicon availability
- Track record of leading technical teams delivering complex infrastructure/models on multi-quarter silicon program timelines
- Applicants must be eligible for any required U.S. export authorizations.
- Strong hands-on experience developing behavioral, functional, or performance models in C++, SystemC, and/or System Verilog
- Deep understanding of FPGA or ASIC architecture fundamentals (fabric architecture, memory subsystems, interconnect, hard IP blocks)
- Familiarity with RTL design and verification flows (SystemVerilog/UVM) sufficient to reason about model-RTL equivalence
- Strong communication skills - able to represent modeling team priorities to architecture leadership and coordinate across verification, design, and software orgs
Nice to have
- Prior experience specifically with FPGA architecture ( embedded memory, transceivers, NoC/interconnect)
- Experience with performance/pathfinding modeling for PPA trade-off studies
- Familiarity with formal methods or golden-model-based verification methodologies
- Experience supporting early software/compiler enablement using pre-silicon models
- Experience delivering customer-consumable pre-silicon models or integrating architectural models into FPGA/ASIC development tools for early customer prototyping
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $231,500 - $341,075 USD
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.