Ambarella Corp.

Ambarella Corp.

Sr. ASIC Design Engineer

US Headquarters · Senior · Full-time

Sponsorship not specified$135k-$170kDetected 30 days ago
PythonNLPLLMsAgentic AIVerilogRoboticsCommunicationProblem Solving

Stay score

odds of building a lasting career here

57Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level III)83
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

Employer immigration record

from this employer's Department of Labor filings

Green-card filing pattern in this occupation

Context, not a finding about this posting: of this employer's 12 green-card filings in this occupation, 92% were for a worker who already held the job.

Files H-1B transfers

2 transfer filings in the last year, covering 2 workers. Median labor-condition decision: 8 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference-alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.

Responsibilities

  • Synthesize and optimize RTL for timing, area, and power.
  • Developing unit level test environments and tests cases
  • Developing front-end methodologies and tool flows.

Requirements

  • Master's degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.
  • Knowledge of System Verilog, Verilog, python, and Perl.
  • Ability to program in scripting languages and the ability to write assembly language programs.
  • Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.

Nice to have

  • Knowledge of logic synthesis and timing closer is a plus

Compensation

  • The base salary range is $135,000 - $170,000.

Benefits

  • Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.

This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.