Ambarella Corp.
Sr. ASIC Design Engineer
US Headquarters · Senior · Full-time
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About the role
- Designing and implementing video compression, image processing, vector computation, and flexible compute systems optimized for future AI agents and large language model (LLM) inference-alongside processor cores and memory subsystems using System Verilog, with a focus on enabling next-generation edge AI markets such as automation, robotics, and intelligent low power embedded systems.
Responsibilities
- Synthesize and optimize RTL for timing, area, and power.
- Developing unit level test environments and tests cases
- Developing front-end methodologies and tool flows.
Requirements
- Master's degree in electrical/Electronics/Computer Engineering with 0-5 years of experience.
- Knowledge of System Verilog, Verilog, python, and Perl.
- Ability to program in scripting languages and the ability to write assembly language programs.
- Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
Nice to have
- Knowledge of logic synthesis and timing closer is a plus
Compensation
- The base salary range is $135,000 - $170,000.
Benefits
- Analyzing and reviewing code coverage and functional coverage and providing recommendations to the verification team to address any gaps.
This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.