Altera
Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead
San Jose, California, United States · Senior
Sponsorship not specified$187k-$270kDetected 9 days ago
PythonBashNode.jsData StructuresAlgorithmsMachine LearningFPGAElectrical EngineeringLeadershipCollaborationMentoring
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odds of building a lasting career here
61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file
Files H-1B transfers
13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- We are in the middle of a genuine modernization: standing up next-generation characterization flows, and onboarding timing sign-off into a new unified flow environment.
- There is meaningful greenfield work here, not just incremental maintenance.
Responsibilities
- You will represent the timing DA domain with design team leads, physical design, technology enablement and QRE partners in cross-functional methodology forums and working groups, and you will drive our engagements with the major EDA vendors - evaluating capabilities, escalating what blocks us, and shaping roadmaps.
- This is a hands-on CAD role: you will develop and release production-grade flows, regressions and automation, then support the design teams running them - triaging tickets, debugging timing issues alongside designers on live tape-outs, and delivering the training and documentation that make the methodology stick.
- Being the technical lead here means influencing the whole chain from transistor-level simulation through characterization to the timing models our design teams and our FPGA software toolchain ship - not just the analysis step in the middle.
- Room to grow your own technical range.
- As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
- We are actively applying AI and ML inside our design automation flows - runtime and resource prediction, corner reduction, knowledge capture from debug.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 10+ years of experience with industry-standard timing analysis, cell characterization, and/or SPICE circuit simulation tools, with the technical depth to evaluate tool capabilities and make methodology decisions.
- If you have ever wanted your timing decisions to reach all the way back into how the models are built, this is that seat.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- 10+ years of professional experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field, with significant hands-on experience developing and deploying production design automation or timing flows.
- 10+ years of experience working with Static Timing Analysis (STA) and timing sign-off methodology, including timing constraints, multi-corner multi-mode (MCMM) analysis, crosstalk, on-chip variation (OCV), timing derates, and advanced process-node timing challenges.
- 10+ years of experience developing automation and software for engineering workflows, including strong proficiency with Python, Tcl, shell scripting, or similar languages, along with a solid understanding of algorithms, data structures, and production-quality software development practices.
- Demonstrated experience owning and releasing production-grade DA/CAD flows, including flow architecture, regression infrastructure, automation, validation, deployment, maintenance, and user support.
- Demonstrated technical leadership in a design automation or timing domain, including setting methodology direction, driving complex technical decisions, establishing best practices, and mentoring engineers without requiring formal management authority.
- Proven experience partnering directly with ASIC, custom IC, physical design, circuit design, or other semiconductor design teams to define methodology requirements, deploy production flows, resolve technical issues, and support designs through tape-out or sign-off.
- Demonstrated ability to lead cross-functional technical initiatives and influence engineering decisions across geographically distributed teams, including collaboration with design, physical design, technology/process, reliability, and EDA vendor organizations.
Nice to have
- Experience owning block-level and/or full-chip STA methodology and timing closure flows through multiple production tape-outs.
- Advanced experience with cell characterization and Liberty model generation, including LVF, POCV, statistical timing, or related variation-aware modeling methodologies.
- Experience with transistor-level timing analysis, custom IP timing, SPICE simulation, or characterization flows.
- Experience with timing reliability, aging, derating, electromigration, or other reliability-aware timing methodologies.
- Experience with advanced-node timing challenges involving variation, signal integrity, crosstalk, multi-voltage designs, low-power methodologies, or complex MCMM sign-off requirements.
- Experience leading technical roadmaps, methodology modernization, or greenfield CAD/EDA infrastructure initiatives across multiple engineering organizations.
- Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Shift 1 (United States of America)
Skills
- About Altera
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $187,000 - $270,000 USD
Company info
- We also offer incentive opportunities that reward employees based on individual and company performance.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.