Broadcom

Broadcom

ASIC Implementation Engineer

USA-CA San Jose Innovation Drive

Sponsorship not specified$144k-$230kDetected 29 days ago
PythonElectrical Engineering

About the role

  • If you already have a Candidate Account, please Sign-In before you apply.
  • This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Responsibilities

  • Own chip floor planning, partition creation, clock tree and delivery of top level partitions
  • Resolve physical design issues related to chip integration and assembly
  • Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team
  • Develop and improve floorplan implementation methodologies using both industry and internal tools
  • Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specification
  • Proven track record with bump planning, RDL implementation, and multi-voltage domain designs
  • Experience in collaborating with design, package and methodology teams during development phase
  • Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division.
  • More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.
  • All subject to relevant plan documents and award agreements.

Nice to have

  • Bachelors in Electrical Engineering and 12+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
  • Or Master's degree in Electrical Engineering and 10+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
  • Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
  • Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes
  • Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning
  • Experience in scripting languages like Python, Tcl, or Perl and EDA tools
  • Additional Job Description:
  • Broadcom offers a competitive and comprehensive

Compensation

  • The annual base salary range for this position is $143,800 - $230,000.
  • As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
  • All subject to relevant plan documents and award agreements.

Benefits

  • Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • Compensation and Benefits

Equal opportunity

  • equal opportunity employer.

Visa & Work Authorization

  • consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other

This listing is sourced directly from Broadcom's careers page and normalized into a canonical job model.