Nuvacore

Nuvacore

CPU Custom Library and Memory Layout Lead

Santa Clara, CA · Senior · Full-time

Sponsorship not specified$200k-$300kDetected 34 days ago
PythonAgentic AIElectrical EngineeringCommunicationCollaboration

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odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

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About the role

  • Lead physical layout of custom library cells (flip-flops, clock-gating cells, level shifters, AOI cells) and custom memory arrays (bit cell arrays, sense amps, decoders, register files) at advanced process nodes - own layout prototyping of critical cells.
  • As a Custom Library and Memory Layout Lead, you will participate in the following:

Responsibilities

  • Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads.
  • As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.
  • Own end-to-end layout closure: floorplanning, logic/SRAM place-and-route, DRC/LVS/antenna clean-up, parasitic extraction hand-off, and mitigation of layout-dependent effects (LDE).
  • Partner with circuit design, Foundry/PDK, CAD, and DFT teams to co-optimize layout for PPA, manufacturability, and yield; validate IP on testchips.
  • Define and drive layout methodology and automation - including P-cell/script-based layout generation and DRC/LVS regression - to raise design efficiency and set team-wide best practices.
  • Manage layout vendors and contractors to scale layout execution across macro designs and cells - scoping work packages, setting quality/schedule targets, and reviewing deliverables for PPA, DRC/LVS, and methodology compliance.

Requirements

  • Hold a BS or MS degree with 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.
  • Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays - bit cells, sense amps, decoders - at advanced CMOS nodes.
  • Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard EDA tools (e.g. Virtuoso, Calibre, StarRC).
  • Strong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit PPA and variation.
  • Experience across the full custom layout flow - floorplanning, cell/bit-cell layout, P-cell/script-based automation, DRC/LVS signoff, and extraction hand-off.
  • Track record delivering production-level standard cell and/or memory layouts through tape-out, with silicon-validated PPA in high-volume products.
  • Experience with testchip layout development and DTCO partnering with foundries at leading-edge nodes.
  • Experience managing external layout vendors/contractors - work scoping, quality/schedule tracking, and technical review - to scale capacity across macro and cell layout programs.
  • Experience using Agentic AI tools for productivity and automation.

Compensation

  • $200k-$300k
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This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.