Broadcom

Broadcom

Design Verification Engineer

USA-CA San Jose Innovation Drive

Work authorization required$144k-$230kDetected 29 days ago
PythonC++Node.jsFPGAHardware DesignCommunicationCollaboration

About the role

  • If you already have a Candidate Account, please Sign-In before you apply.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.
  • Broadcom is proud to be an equal opportunity employer.

Responsibilities

  • End-to-End Verification: Lead and execute comprehensive verification strategies at both the block and system levels.
  • Methodology Architecture: Define, deploy, and enhance advanced ASIC design verification flows and DV methodologies.
  • Environment Development: Build robust, scalable, object-oriented verification environments and testbenches.
  • Debug & Analysis: Independently debug complex design and verification issues
  • Debug & Analysis: Independently debug complex design and verification issues; analyze and resolve intricate verification trade-off scenarios.
  • Define, deploy, and enhance advanced ASIC design verification flows and DV methodologies.
  • Build robust, scalable, object-oriented verification environments and testbenches.
  • Independently debug complex design and verification issues; analyze and resolve intricate verification trade-off scenarios.
  • All subject to relevant plan documents and award agreements.

Requirements

  • Frameworks & Languages: Strong working knowledge of object-oriented verification languages UVM, C/C++, and scripting languages ( Perl, Python, or Tcl ).
  • Work Authorization: Must have legal authorization to work in the US.
  • Experience with hardware design, hardware debugging, and SystemC or other programming languages.
  • Hands-on experience with hardware emulation (e.g., Palladium, Zebu) and FPGA-based prototyping.
  • If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
  • Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or a related field.
  • Strong working knowledge of object-oriented verification languages UVM, C/C++, and scripting languages ( Perl, Python, or Tcl ).

Skills

  • Lead ASIC Design Verification Engineer
  • Experience working with advanced process node technologies (e.g., 5nm and below ) is highly desired.

Compensation

  • The annual base salary range for this position is $143,800 - $230,000.
  • As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
  • All subject to relevant plan documents and award agreements.

Benefits

  • Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • Compensation and Benefits
  • Cross-Functional Collaboration: Partner closely with design and verification teams to ensure alignment on coverage, timelines, and architectural goals.

Equal opportunity

  • equal opportunity employer.

Visa & Work Authorization

  • Work Authorization: Must have legal authorization to work in the US.
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This listing is sourced directly from Broadcom's careers page and normalized into a canonical job model.