K2 Space

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · Senior

Sponsorship not specifiedDetected 20 days ago
PythonC++GitCI/CDVerilogEmbedded SystemsElectrical EngineeringManual Testing

About the role

  • This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Engage external IP providers and verification partners when needed.
  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

Requirements

  • 5+ years of experience in ASIC/SoC verification.
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
  • Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Nice to have

  • Experience with developing and integrating reference models.
  • Understanding of low power verification.
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Benefits

  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
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