Microchip Technology
Sr Tech Staff Engineer - Design (Signal & Power Integrity)
San Jose, CA, United States · Staff+
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($91,000) is below the Level I prevailing wage of $117,998. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $141,835 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Mechanical Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Mechanical Engineers (17-2141) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Green-card follow-through: 33%
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Microchip Technology Inc. is a leading provider of embedded control applications.
- We also license Flash-IP solutions that are incorporated in a broad range of products.
- You will be working with other SIPI engineers and working with a global cross functional team to provide solutions at a system level for internal and external customers.
Responsibilities
- Understand channel loss mechanisms, interpret and optimize eye diagrams, and apply jitter analysis and mitigation techniques.
- Possess a comprehensive grasp of Power Delivery Network (PDN) design and optimization.
- Conduct extensive SIPI simulations (pre-layout and post-layout) to optimize signal integrity and power integrity performance at a system level.
- Implement and maintain robust SI/PI strategies throughout the product development lifecycle (die and package).
- Proactively identify and address potential SIPI issues early in the design process.
- Stay abreast of the latest industry trends, emerging tools, and methodologies in SIPI, PDN design, and SerDes transceiver development.
- Develop and refine methodologies for running simulations to ensure robust and reliable PDN systems.
- Develop strategies and methodologies to guarantee robust performance of high-speed SerDes transceivers, including equalization techniques and advanced jitter analysis.
- How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization?
- People come to work at Microchip because we help design the technology that runs the world.
Requirements
- Bachelor of Science (BS) degree in Electrical Engineering or Electronic --Engineering
- 15+ years of relevant experience
- Demonstrated experience in resolving SI/PI-related challenges, including Power Delivery Network (PDN) optimization and noise mitigation.
- Proficiency in analyzing and optimizing signal and power integrity across different levels of integration.
- Expertise in via modeling, connector Time Domain Reflectometry (TDR) analysis, and stack-up analysis.
- Strong, hands-on experience with industry-standard Field Solvers: Ansys HFSS, Ansys Siwave, Mentor Graphics Hyperlynx, and HSPICE, Redhawk
- Experience with simulation tools: Keysight ADS and Mentor Graphics Hyperlynx for pre- and post-layout simulation and analysis.
- Hands-on experience with Vector Network Analyzers (VNAs), Time Domain Reflectometers (TDRs), Sampling and Real-Time Oscilloscopes, Bit Error Rate Testers (BERTs), de-embedding techniques, and jitter analysis equipment.
Nice to have
- Experience with IBIS-AMI modeling, validation, and correlation is a significant plus.
- Master of Science (MS) degree in a relevant engineering field is preferable.
- Physical Attributes:
- Feeling, Hearing, Reaching, Seeing, Talking, Works Alone
- Experience in performing package analysis and optimization (thermal and mechanical considerations) is a plus.
Compensation
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive base pay, restricted stock units, and quarterly bonus payments.
- The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.*
- Want to join a 20,000-member team that works on the technology that powers the world around us?
Benefits
- Benefits of working at Microchip
- In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.
- Find more information about all our benefits at the link below:
- Visit our careers page to see what exciting opportunities and company perks await!
Company info
- Are you looking for a unique opportunity to be a part of something great?
- We offer all that and more at Microchip Technology, Inc.
- Collaborate effectively within a global team environment, demonstrating excellent communication skills (verbal and written).
- Collaborate effectively with external partners, suppliers, and customers on SI/PI-related topics.
Equal opportunity
- Microchip Technology Inc is an equal opportunity/affirmative action employer.
- equal opportunity/affirmative action employer.
This listing is sourced directly from Microchip Technology's careers page and normalized into a canonical job model.