Altera
Physical Design Engineer
San Jose, California, United States · Mid
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($118,900) is below the Level I prevailing wage of $124,405. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Ability to work effectively in a fast-paced, collaborative semiconductor development environment.
Responsibilities
- Perform block-level physical design implementation of custom IP and SoC designs from RTL through GDSII, supporting the delivery of manufacturing-ready design databases.
- Execute and support stages of the physical design flow, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing analysis, and physical optimization.
- Perform static timing analysis (STA) and help resolve setup, hold, signal integrity, and other timing violations to achieve design closure.
- Support the development and optimization of clock distribution networks, power distribution networks, and multiple power domain implementations to meet performance, power, and reliability targets.
- Participate in physical verification and signoff activities, including formal equivalence checking (LEC), static timing analysis, power integrity, IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), and structural verification.
- Analyze physical design results, identify root causes of implementation issues, and work with senior engineers and cross-functional teams to implement corrective actions.
- Optimize physical implementations to improve product-level metrics including performance, power consumption, frequency, area (PPA), manufacturability, and reliability.
- Collaborate closely with RTL, Logic Design, DFT, CAD, Architecture, Verification, and Product Engineering teams throughout the design cycle.
- Support Design-for-Test (DFT) integration and implementation throughout physical design and signoff.
- Support physical design convergence across multiple design iterations while balancing timing, power, congestion, and area tradeoffs.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline and 3+ years of experience in semiconductor Physical Design.
- 3+ years of experience with physical design implementation of custom IP or SoC designs from RTL through GDSII.
- 3+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.
- 2+ years of experience performing static timing analysis (STA) and supporting timing closure on semiconductor designs.
- 2+ years of experience with physical verification and signoff activities, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and/or power integrity analysis.
- Strong understanding of semiconductor physical implementation methodologies and design flows.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
Nice to have
- Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Experience with advanced technology nodes (7nm, 5nm, 3nm, or smaller).
- Experience with Tcl, Python, Perl, or Shell scripting for flow automation.
- Knowledge of static timing analysis and low-power implementation methodologies, including UPF/CPF.
- Experience with Synopsys, Cadence, or Siemens EDA physical design and analysis tools.
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
Skills
- About Altera
- Strong analytical and debugging skills for solving timing, congestion, and physical implementation challenges.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $118,900 - $169,000 USD
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.