Hewlett Packard Enterprise

Hewlett Packard Enterprise

Senior Design Verification Engineer

Sunnyvale, California, United States of America · Senior

Sponsorship not specified$154k-$311kDetected 4 hours ago
PythonCI/CDMachine LearningLLMsCadenceFPGAVerilogElectrical EngineeringTCP/IPCommunicationProblem Solving

About the role

  • We know varied backgrounds are valued and succeed here.
  • We make bold moves, together, and are a force for good.
  • A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale.

Responsibilities

  • Develop and execute verification plans for IP-level and system-level designs.
  • Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation.
  • Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
  • Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
  • Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.
  • Support software and firmware teams with early bring-up activities on emulation platforms.
  • 5 - 8 years of professional experience in design verification of digital/mixed-signal designs.
  • Senior Design Verification Engineer
  • Any reliance on fraudulent communication is at the individual's own risk, and HPE disclaims legal liability for any resulting damages.
  • We have the flexibility to manage our work and personal needs.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • Strong proficiency in SystemVerilog and UVM methodology.
  • Hands-on experience with emulation-based verification platforms (e.g., Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).
  • Proficiency in debugging complex hardware designs using simulation and emulation tools.
  • Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.

Nice to have

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.
  • Knowledge of communication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.
  • Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).
  • Familiarity with FPGA prototyping platforms and flows.
  • Experience with power-aware verification (UPF/CPF).
  • Prior exposure to SoC-level verification or full-chip integration verification.
  • Knowledge of processor architectures (ARM, RISC-V, x86) and software-driven verification techniques.

Skills

  • "The expected salary/wage range for this position is provided below.
  • Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

Compensation

  • USD 153,500 - 310,500 in California
  • The listed salary range reflects base salary.

Benefits

  • Health & Wellbeing
  • Build, maintain, and enhance UVM/ SystemVerilog -based testbench environments including scoreboards, monitors, drivers, and coverage models.
  • Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.

Company info

  • Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
  • Job Description:
  • We are seeking a talented and driven Senior Design Verification Engineer with specialized knowledge and experience in emulation - based verification to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.
  • Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.
  • We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
  • Our culture thrives on finding new and better ways to accelerate what's next.
  • If you are looking to stretch and grow your career our culture will embrace you.
  • Open up opportunities with HPE.
  • We are seeking a talented and driven Senior Design Verification Engineer with specialized knowledge and experience in emulation - based verification to join our engineering team.
  • In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out.
  • You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure.

Equal opportunity

  • Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
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This listing is sourced directly from Hewlett Packard Enterprise's careers page and normalized into a canonical job model.