Duo Security

ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)

San Jose, California, United States of America · Full-time

Sponsorship not specified$184k-$264kDetected 29 days ago

ANSYSCadenceElectrical EngineeringHardware DesignCisco

About the role

The application window is expected to close on: 09/25/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States.
Join us to power the future of the digital world.

Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.
Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.

SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.

Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
Experience with die-to-die interfaces (UCIe or proprietary).
Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
Working knowledge of Vector Network Analysis.
Basic knowledge of IBIS.
We work as a team, collaborating with empathy to make really big things happen on a global scale.
Because our solutions are everywhere, our impact is everywhere.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan.
The applicable full salary ranges for this position, by specific state, are listed below:

Please see the Cisco careers site to discover more benefits and perks.
Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.

$163,600.00 - $269,800.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
Cisconians power the future.
We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale.
The depth and breadth of our technology doesn't just benefit our customers - it also means limitless opportunities for us to experiment and learn.
We understand the power each of our unique backgrounds bring when we work together.
Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life's best work.
We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

This listing is sourced directly from Duo Security's careers page and normalized into a canonical job model.