Etched
Formal Verification - DV
San Jose · Staff+
Sponsorship not specifiedDetected 42 days ago
PythonNLPCadenceVerilogResearch
About the role
- We are seeking a Formal Verification Engineer to join our ASIC Design Verification team.
- You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers.
- You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip.
Responsibilities
- Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
- Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
- Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
- Work with architects and RTL designers to translate design intent and specifications into high-value formal and closure criteria.
- Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
- Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.
- 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.
- Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
- Relocation support for those moving to San Jose (Santana Row)
Requirements
- Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
- Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
- Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
- Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
Company info
- We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes.
- We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.
This listing is sourced directly from Etched's careers page and normalized into a canonical job model.