Etched

Design Verification Engineer - SoC

Austin · Staff+

Sponsorship not specifiedDetected 97 days ago

PythonData AnalysisNLPVerilogResearch

About the role

You will ensure the custom IPs powering our chips - including systolic arrays, DMA engines, and NoCs - are robust, high-performance, and silicon-ready.

Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
Improve and maintain the architectural performance models.
Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
Develop SystemVerilog or Python-based checkers for verifying the performance features.
Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

Strong understanding of digital design, RTL, and ASIC design flows.
Hands-on experience with performance verification, simulation, and modeling.
Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
You may be a good fit if you have

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Various wellness benefits covering fitness, mental health, and more
Develop coverage monitors and analyze coverage to ensure all performance features are covered.
Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.

We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.

This listing is sourced directly from Etched's careers page and normalized into a canonical job model.