Astera Labs Inc.
Digital Design Manager
Toronto, Ontario, Canada · Senior
Stay score
odds of building a lasting career here
Thin sponsorship signal and lottery-bound (~15% per draw). A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- The role offers hands-on technical ownership, opportunities to mentor engineers, and direct influence on products that keep next-generation AI systems connected, observable, and reliable.
Responsibilities
- Partner with design and physical design teams to balance DFT area, timing, routing, and manufacturability.
- Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.
- Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.
- Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 10-15 years of experience in Digital Design engineering or related semiconductor design and test work.
- Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.
- Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.
Nice to have
- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.
- Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.
- Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.
Skills
- DFT Architecture & Planning
- DFT Implementation & Silicon Readiness
- Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.
- Quality, Yield & Diagnostics
- Improve diagnostic capabilities for silicon, package, and system-level issues.
- Technical Leadership & Collaboration
- Mentor DFT engineers and coordinate execution across product development milestones.
- Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.
Compensation
- Salary range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need.
Benefits
- Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.
- Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.