Astera Labs Inc.
Principal Electrical Design Engineer
San Jose, California, United States · Principal · Full-time
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$4,072 more — $189,072 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $189,072 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electrical Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electrical Engineers (17-2071) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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from this employer's Department of Labor filings
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Define and evolve hardware implementation strategies for management and control interfaces such as I2C, SPI, GPIO, MDIO, and debug and observability architectures
- Serve as the technical authority for board-level hardware development across high-performance server and connectivity platforms, including NIC cards, PCIe add-in cards, and chassis-integrated hardware
- This role encompasses complex hardware systems including chassis boards, NIC cards, PCIe Gen6 platforms, and 800G Ethernet products.
Responsibilities
- Define and own the board-level hardware architecture and technical roadmap across multiple product lines and platform generations
- Establish design standards, methodologies, and best practices that scale across the hardware engineering organization
- Drive architectural tradeoff decisions for complex multi-layer PCBs integrating high-speed digital, analog, and mixed-signal circuitry, balancing performance, cost, schedule, and manufacturability
- Get involved and drive discussions on stack-up strategy, impedance optimization and other SI relates development work
- Own power delivery architecture strategy including multi-rail regulation topologies, advanced sequencing schemes, transient response optimization, protection philosophies, and power budgeting across platform generations
- Electrical Design Ownership
- Own schematic capture and board-level design for complex multi-layer PCBs with high-speed digital, analog, and mixed-signal circuitry
- Provide technical oversight and approval for schematic capture and board-level designs across multiple designs
- Lead component strategy and qualification roadmaps in partnership with suppliers, sourcing, and manufacturing teams
- Drive design-for-excellence initiatives including DFT, DFM, and DFR to systematically improve manufacturability, yield, reliability, and production readiness across all programs
Requirements
- 12+ years of progressive hardware design experience with deep expertise in board-level electrical engineering and demonstrated technical leadership across multiple product generations
- Extensive track record of architecting and delivering production hardware for server, networking, storage, or high-performance compute systems at scale
- Expert-level experience with high-speed SerDes-based systems supporting Ethernet, PCIe, or related protocols
- deep hands-on experience with PCIe Gen5/Gen6 and 400G/800G Ethernet system design
- Proven track record leading hardware bring-up and debug of complex platforms using oscilloscopes, protocol analyzers, and advanced lab instrumentation
- Strong track record of mentoring engineers and elevating team capabilities
Nice to have
- Experience defining architecture for NIC cards, accelerator cards, or other PCIe add-in card platforms across multiple generations
- Deep expertise with 800G Ethernet and emerging 1.6T electrical interfaces and system integration challenges
- Experience architecting solutions using retimers, redrivers, advanced clocking architectures, and high-speed interconnect subsystems
- Expertise in compliance and validation workflows for PCIe and Ethernet platforms, including contributions to industry specifications or standards bodies
- Experience driving contract manufacturer relationships, production ramp strategies, and yield optimization for complex hardware products
- Scripting and automation proficiency in Python or similar languages for lab automation, measurement analysis, hardware characterization workflows, and design flow optimization
- Experience influencing product strategy and roadmap decisions at the organizational level
- Bachelor's or Master's degree in Electrical Engineering or a closely related field
Skills
- Labs (NASDAQ:
- ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Discover more at www.asteralabs.com.
Compensation
- Base pay range for this role is $185,000 - $240,000.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.