Nuvacore

Nuvacore

CPU Design Verification Lead

Austin, TX · Senior

Sponsorship not specified$200k-$300kDetected 35 days ago
PythonC++Thermal AnalysisVerilogCommunicationMentoring

Stay score

odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level IV · 4×
Level I$100,1311 entry
Level II$126,2352 entries
Level III$152,3603 entries
Level IV$178,4644 entries

This range already reaches Level IV — the maximum four lottery entries.

DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · Austin-Round Rock-San Marcos, TX. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

8 transfer filings in the last year, covering 8 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • Test and debug the performance of a CPU against the performance model.
  • Writing tests in ASM, C, C++, or other to test the CPU's correctness according to the test plan

Responsibilities

  • Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads.
  • As Design Verification Lead you will lead the team verifying functionality and correctness of the CPU design.
  • As a CPU Design Verification (DV)
  • Building test environments which target every aspect of the CPU unit, core, or system. Your goal is to find every weakness and flaw in the design using proven verification techniques.
  • As a CPU Design Verification (DV) Lead, you will lead the team that is driving efforts in all the following areas:
  • Your goal is to find every weakness and flaw in the design using proven verification techniques.
  • Develop methodology and flows for running simulations and generate all regression results and debug information.
  • Triage issues and write up detailed bug reports to assist the CPU design team in fixing design issues.
  • Develop and write detailed test plans for the CPU units, core, or system.
  • Develop DV methodologies and best practices for the team.

Requirements

  • BS or MS with 15+ years experience in CPU verification
  • Experience with one or more of RISC-V, ARM64, or x86 ISA
  • Experience in C, C++, System Verilog, scripting and other languages such as Perl or Python
  • Experience managing and mentoring DV engineers
  • Expertise in one or more areas of CPU microarchitecture including instruction fetch, branch prediction
  • Strong background in low power microarchitecture and high-performance verification techniques, with a proven track record of verification and sign-off on multiple CPU programs.

Compensation

  • $200k-$300k

Benefits

  • Create test stimulus and relevant coverage metrics at both the unit and top level that fully stresses all corners of the design

Company info

  • Develop golden models and checkers at unit and top level as part of test bench infrastructure

This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.