Altera

Altera

FPGA Compiler (Placer) Engineer

San Jose, California, United States

Sponsorship not specified$149k-$216kDetected 28 days ago
PythonC++Data StructuresAlgorithmsFPGAElectrical EngineeringCollaboration

About the role

  • Job Details: Job Description: About Altera At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
  • Position Overview Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications.
  • Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA.

Responsibilities

  • Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
  • Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
  • Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
  • Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
  • drive improvements to convergence and design closure.
  • Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
  • Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.
  • Collaborate with world-class teams across architecture, silicon, and software

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields.
  • Experience in algorithms and data structures (optimization, graph theory, heuristics)
  • Experience with placement algorithms or physical design flows
  • Experience in C/C++ and software engineering best practices
  • Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering)
  • Experience with Timing-driven and congestion-driven optimization
  • Experience in solving complex, large-scale optimization problems with high performance and scalability requirements.
  • Applicants must be eligible for any required U.S. export authorizations.
  • Experience in ASIC or FPGA physical design methodologies

Nice to have

  • Experience with FPGA toolchains (e.g., Quartus, Vivado )
  • Knowledge of FPGA architectures and interconnect fabrics
  • Familiarity with routing and timing closure techniques
  • Experience with parallel or distributed algorithms for EDA tools
  • Scripting experience (e.g., Python, Tcl ) for tooling and automation
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:

Skills

  • About Altera
  • Position Overview
  • Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
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This listing is sourced directly from Altera's careers page and normalized into a canonical job model.