Astera Labs Inc.
Principle Design Verification Engineer SerDes/PHY
San Jose, California, United States
Sponsorship not specified$207k-$230kDetected 4 days ago
PythonVerilogElectrical EngineeringFDA RegulatoryLeadership
About the role
- This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story.
Responsibilities
- Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
- Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
- Model and validate channel behavior, link training state machines, and analog handoff scenarios
- Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
- Expert-level proficiency in SystemVerilog and UVM
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering
- Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
- Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
- Scripting proficiency in Python or Perl for verification automation and regression management
Skills
- Verification Architecture & Strategy
- Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
- Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
- Execution & Coverage Closure
- Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
- Physical Layer & Protocol Verification
- Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards
- Cross-Functional Leadership
- Mentor junior DV engineers and set technical direction across the verification team
- Contribute to verification IP reuse strategy and tooling improvements across product lines
Compensation
- Salary range is $207,000 to $230,000 depending on experience, level, and business need.
Benefits
- Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out
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