Altera
Senior Backend Design Automation Engineer — New Process Node Enablement
San Jose, California, United States · Senior
Sponsorship not specified$149k-$216kDetected 10 days ago
PythonBashNode.jsData StructuresAlgorithmsLinuxMachine LearningCadenceFPGAElectrical EngineeringPublic Speaking
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odds of building a lasting career here
61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file
Files H-1B transfers
13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Every new process node arrives as a PDK, a standard-cell library, and a set of technology collateral that nothing in our flow stack has seen before.
- A senior engineer joining now will have the opportunity to shape how the next several process nodes are enabled.
Responsibilities
- Own the end-to-end bring-up, qualification, and production deployment of Back-End design automation flows for new process nodes and technology releases.
- Partner directly with design leads, domain representatives, and technology enablement teams to understand new-node requirements and translate them into scalable Back-End methodologies and flows.
- Develop, maintain, and execute comprehensive regression test cases to validate Back-End flow functionality, identify failures, and drive issues through resolution prior to production release.
- Support Back-End design teams through production use and tape-out, including flow deployment, debug, user support, training, documentation, and methodology improvements.
- Contribute to the modernization and consolidation of Back-End construction, verification, and analysis flows within a unified design automation environment with managed workspaces and released collateral.
- Collaborate with globally distributed Design Automation teams and engineering experts to drive technical alignment, resolve cross-functional issues, and enable new process nodes across multiple projects.
- As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
- New node bring-up and project support are the core of the job, not a side project.
- You will work with other Design Automation teams and engineering experts across the globe to enable new process nodes for new projects.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field, with 8+ years of professional experience in Back-End IC design or design automation.
- 8+ years of professional experience using industry-standard Back-End EDA tools, including tools from Synopsys, Cadence, and/or Siemens.
- 8+ years of professional experience driving technical alignment across geographically distributed engineering teams, including coordinating technical decisions and execution across multiple sites and time zones.
- Integrate and qualify new PDKs, standard-cell libraries, Foundation IP, and other technology collateral, updating EDA tool configurations, flow scripts, and supporting infrastructure as required.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- 8+ years of professional experience owning, developing, or supporting production Back-End design flows, including areas such as PDK installation and setup, custom design construction, circuit simulation, cell characterization, physical verification (DRC/LVS), RC extraction, static timing analysis, IR/EM, or power analysis.
- 8+ years of professional experience working with semiconductor process technologies, including direct experience bringing up or migrating design environments to new process nodes or technology releases, including PDK, standard-cell library, and technology collateral integration and qualification.
- 8+ years of professional experience developing and maintaining software and automation for semiconductor design flows, including Python, Tcl, shell scripting, or similar languages, with a strong understanding of algorithms and data structures and experience releasing production flows through a formal process.
- 8+ years of professional experience working in Linux/UNIX environments with distributed compute infrastructure and job schedulers, including efficiently executing and managing large-scale design and regression workloads.
- 8+ years of professional experience partnering directly with IC design teams as internal customers, including gathering methodology requirements, deploying production flows, supporting users through tape-out, and developing technical training and documentation.
- 8+ years of professional experience communicating complex technical concepts to engineering audiences, including presenting Design Automation methodology proposals, technical recommendations, and project status to design leads and senior engineering management.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,925 USD
Company info
- We are actively applying AI and ML inside our design automation flows, including runtime and resource prediction, automated failure summarization and categorization in regressions, and knowledge capture from debug.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.