Ciena
Layout Design Intern (Fall 2026)
Ottawa · Intern · Internship
Sponsorship not specified$26k-$35kDetected 9 days ago
CadenceElectrical EngineeringHardware DesignLeadership
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odds of building a lasting career here
32Risky
Cap-exempt (no lottery)0
Sponsors this role62
Entry-level history0
PERM / green-card track0
Lottery odds (Level I)39
Fits your clock70
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About the role
- Work term of 4 months starting in Spetember/October 2026.
- The WaveLogic™ family of products is a cornerstone of Ciena's optical fiber transmission solutions and a key contributor to the company's leadership in the global telecommunications industry.
- The role offers the opportunity to contribute to next-generation high-speed circuit development in a collaborative engineering environment.
Responsibilities
- This opportunity provides hands-on exposure to advanced high-speed analog and mixed-signal circuit design within a team that has contributed to more than three decades of innovation in broadband fiber-optic modems.
- Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade-offs and layout strategies for high-speed circuits
- Develop custom layouts for advanced analog and mixed-signal blocks, following structured methodologies for floorplanning, placement, and routing
- Execute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability
- Collaborate closely with circuit designers and layout engineers to identify and resolve layout-related risks early in the design cycle
- Provide clear status updates and participate in team meetings, design discussions, and knowledge-sharing activities
- Exposure to high-speed data converter or phase-locked loop (PLL) layout design
- Experience collaborating in cross-functional hardware design teams
- At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.
- Familiarity with semiconductor manufacturing processes and foundry design rules
Requirements
- Hands-on experience with custom analog and mixed-signal layout design in deep sub-micron complementary metal-oxide semiconductor (CMOS) technologies
- Ability to interpret and debug DRC and LVS reports effectively
- Familiarity with bipolar CMOS (BiCMOS) technologies
- Strong analytical skills with the ability to proactively identify layout-sensitive circuit structures
- Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations
Skills
- Experience using industry-standard layout tools such as Cadence Virtuoso and Siemens Calibre
Compensation
- The hourly pay rate for this position is $25.50 - $35.00
- Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business.
- Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
- In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.
Equal opportunity
- If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
This listing is sourced directly from Ciena's careers page and normalized into a canonical job model.