Altera

Altera

Physical Design Implementation and STA Lead

San Jose, California, United States

Sponsorship not specified$149k-$215kDetected 4 days ago
PythonBackend DevelopmentMachine LearningFPGAElectrical EngineeringLeadershipCollaboration

About the role

  • This is a highly technical individual contributor role with project leadership responsibilities.
  • Contribute to methodology improvements and implementation best practices.
  • Identify and resolve setup, hold, recovery, removal, SI/crosstalk, and clock-related timing violations.

Responsibilities

  • Physical Design Implementation
  • Lead block-level physical implementation including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure.
  • Support SoC-level physical implementation and collaborate on floorplanning, partitioning, and integration strategies.
  • Develop and maintain implementation constraints including SDC and UPF to achieve timing, power, and area (PPA) goals.
  • Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
  • Drive implementation convergence across timing, power, congestion, and routability objectives.
  • Lead static timing analysis (STA) and timing closure across multiple process, voltage, and temperature corners (MMMC).
  • Perform timing analysis using Synopsys PrimeTime or equivalent STA tools.
  • Drive timing-driven ECO implementation in collaboration with RTL and physical design teams.
  • Develop timing constraints and validate timing exceptions to ensure robust signoff quality.

Requirements

  • 7+ years of experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products.
  • 5+ years of experience performing block-level physical implementation including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), optimization, and ECO closure.
  • 3+ years of experience performing static timing analysis using Synopsys PrimeTime or equivalent STA tools, including multi-mode multi-corner (MMMC) timing analysis.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.

Nice to have

  • Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • 10+ years of experience in physical design and static timing analysis for advanced semiconductor products.
  • Experience with advanced process technologies including 7nm, 5nm, or below.
  • Experience with SoC physical implementation and top-level timing closure.
  • Experience with high-speed interface implementation including PCIe, Ethernet, SerDes, DDR, LPDDR, HBM, or similar technologies.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:

Skills

  • About Altera

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $149,100 - $215,000 USD
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This listing is sourced directly from Altera's careers page and normalized into a canonical job model.