Ambarella Corp.
ASIC Design Engineer Intern
US Headquarters · Intern · Internship
Stay score
odds of building a lasting career here
Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Designing and implementing video compression logic, image processing logic, neural network and AI accelerator logics, and processor cores, in Verilog and System Verilog.
Responsibilities
- Synthesize and optimize RTL for timing, area and power.
- Developing front-end methodologies and tool flows.
Requirements
- Master's degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
- Knowledge of System Verilog, Verilog, and Perl.
- Ability to program scripting languages and the ability to write assembly language programs.
- Knowledge of logic synthesis and timing closer
- Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
Benefits
- Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.
- Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.
This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.