credosemi

credosemi

Principal ASIC Design Engineer

San Jose, California · Principal

Sponsorship not specified$180k-$210kDetected 11 days ago
PythonCode ReviewVerilogElectrical EngineeringCommunicationCollaborationProblem Solving

About the role

  • Credo is engineering the future of high-speed connectivity for the AI-driven world. With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers.
  • Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure.

Responsibilities

  • Design, implement, and debug complex logic blocks.
  • Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
  • Participate in design and code reviews to ensure quality.
  • Develop functional tests/testbenches and run RTL and gate-level simulations.
  • Work with verification, DFT, and physical design engineers to achieve successful tape-outs.
  • Bring up, validate, and debug chip features
  • collaborate with software, firmware, and systems teams.
  • Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams.
  • As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks.
  • You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.

Requirements

  • BS/MS degree in Electrical Engineering or Computer Science.
  • Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
  • Proficiency in Verilog/SystemVerilog RTL design.
  • Knowledge of synthesis and static timing analysis.
  • familiarity with UVM.
  • Experience with gate-level simulations, chip bring-up, and validation.
  • Proven track record of successful production tape-outs.

Nice to have

  • Expertise in scripting languages (Python, Tcl, Perl, Shell).
  • Hands-on experience with STA and timing closure.
  • Strong problem-solving and planning skills.
  • Excellent communication and collaboration abilities.
  • Credo is an Equal Opportunity Employer.

Skills

  • Credo is engineering the future of high-speed connectivity for the AI-driven world.

Compensation

  • The base salary range for this position is $180,000 – $210,000 a year.
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