Butterfly Network
Distinguished Engineer, ASIC (CONTRACT)
Burlington, MA Office; California - Hybrid; New York, NY Office; Other · Contract
No sponsorshipDetected 8 days ago
SparkBudgetingVerilogSignal ProcessingUnityRadiologyCollaboration
About the role
- Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions.
- Butterfly first proved its technology in the point-of-care ultrasound market - commercializing the world's first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™.
- Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative.
Responsibilities
- The role of the Distinguished Engineer, Digital ASIC Designer offers the opportunity to work within the heart of the product development team to own the core of what will set Butterfly Network apart.
- This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.
Requirements
- Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs.
- Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs.
- Candidates must be authorized to work in the United States.
- Baseline skills/experiences/attributes:
- 8-12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership.
- Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
- Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
- Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.
- Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.
- Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware-firmware interfaces (register maps, control/status paths, data-plane contracts).
- Ideally, you also have these skills/experiences/attributes (but it's ok if you don't!):
Skills
- BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
- Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP.
- Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths).
- Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.
- Company Description
- Let's build something extraordinary together!
Company info
- Our mission is THE mission.
Visa & Work Authorization
- Candidates must be authorized to work in the United States.
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This listing is sourced directly from Butterfly Network's careers page and normalized into a canonical job model.