Cadence
DFT Design Engineer
AUSTIN
No sponsorshipDetected 9 days ago
CadenceVerilogProblem Solving
About the role
- Should follow systematic quality metrics driven ATPG pattern generation.
Responsibilities
- Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
- Intimate knowledge of memory build-in self-test (MBIST)
- Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers
Requirements
- It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
- US citizenship Required
- Prior experience with Cadence tools and flows is highly desirable
Benefits
- Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
- Debug and Analysis of failures to improve fault coverage
- Knowledge of timing analysis and equivalency checks would be added bonus
Visa & Work Authorization
- US citizenship Required
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This listing is sourced directly from Cadence's careers page and normalized into a canonical job model.