Altera
Senior DFT Design Engineer
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$32,315 more — $219,315 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $219,315 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Architectural and Engineering Managers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Architectural and Engineering Managers (11-9041) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes.
Responsibilities
- Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.
- Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.
- Collaborate with IP and integration design teams to align DFT features with design functionality and timing.
- Partner with test development teams to support silicon bring-up, debug, and production readiness.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience in the following - OR.
- Master's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of industry experience in the following:
- 8+ years of experience in DFT design and verification at both RTL and gate level.
- Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools
- Design automation experience and proficiency in scripting languages such as Perl/TCL
- Applicants must be eligible for any required U.S. export authorizations.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience in the following - OR - Master's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of industry experience in the following:
Nice to have
- Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.
- Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $187,000 - $270,700 USD
Benefits
- Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.
Company info
- The Altera DFT team is looking for a motivated DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.