Etched
Design Verification Engineer - Internal IP
Austin · Staff+
Sponsorship not specifiedDetected 97 days ago
PythonNLPVerilogResearchProblem Solving
About the role
- You will ensure the custom IPs powering our chips - including systolic arrays, DMA engines, and NoCs - are robust, high-performance, and silicon-ready.
Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
- Work closely with architects and designers to validate functionality and design intent.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
Requirements
- Proficiency with UVM and SystemVerilog.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
- Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
- You may be a good fit if you have
- Strong candidates may also have experience with
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
- Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
Company info
- We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes.
- We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.
This listing is sourced directly from Etched's careers page and normalized into a canonical job model.