Nuvacore

Nuvacore

CPU Custom Memory Design - SRAMs and Register Files

Austin, TX · Senior

Sponsorship not specified$140k-$200kDetected 34 days ago
PythonAgentic AIElectrical EngineeringCommunicationCollaboration

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odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

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About the role

  • As a Custom Memory Design Engineer, you will participate in the following:
  • Define and drive adoption of Tools, Flows, and Methodology (TFM) - including characterization automation and compiler QA - to raise design efficiency and set team-wide best practices.

Responsibilities

  • Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads.
  • As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.
  • Own schematic development and characterize custom memories (SRAM, register files) to optimize PPA at advanced process nodes.
  • Supervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.
  • Own end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.
  • Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom memories for downstream design PPA.
  • Collaborate closely with RTL, providing explicit custom memory functional specifications, timing behaviors, and state definitions to support accurate RTL modeling.

Requirements

  • Hold a BS or MS degree with 8+ years of experience in custom memory circuit design: SRAMs, and/or Register files.

Nice to have

  • SRAMs, and/or Register files.
  • Hands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays - bit cells, sense amps, decoders - in advanced CMOS nodes.
  • Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cell architectures.
  • Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.
  • Deep understanding of end-to-end signoff for custom memories - DRC/LVS/antenna, extraction, SPICE margins, STA, EM/IR - and characterization flows spanning timing, power, and noise.
  • Proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.
  • Demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.
  • Experience partnering directly with foundries on PDK bring-up and device co-optimization (DTCO) at leading-edge nodes.

Compensation

  • $140k-$200k
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This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.