Phizenix
Digital Design Engineer
Santa Clara, CA
Sponsorship not specified$180k-$250kDetected 2 days ago
PythonSignal ProcessingCommunication
About the role
- We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon.
- Strong digital ASIC fundamentals, paired with the ability to debug complex designs in emulation and on silicon, round out the profile.
- Just as important, the ideal candidate leverages strong firmware coding experience to drive pre-silicon simulation, develop bare-metal diagnostics, and ensure seamless hardware-software integration-for example, writing firmware on an embedded RISC CPU IP to control on-chip analog hardware blocks and low-speed control/calibration loops for optical components.
Responsibilities
- Develop micro-architecture and author high-quality, synthesizable RTL following best-in-class coding methods and design-for-verification / design-for-test practices.
- Drive pre-silicon simulation and hardware-software co-verification, validating firmware against RTL well ahead of tape-out.
- Drive the full implementation flow: synthesis, timing constraints (SDC), timing closure, and equivalence checking (Formality / Conformal), with clean Lint / CDC / RDC signoff.
- Build and run emulation environments
- lead silicon bring-up sequences and post-silicon debug, root-causing and resolving issues on hardware.
- Provide responsive support-triaging design problems and delivering timely solutions-and collaborate with analog/mixed-signal, DSP, verification, and physical-design teams.
- Build and run emulation environments; lead silicon bring-up sequences and post-silicon debug, root-causing and resolving issues on hardware.
- You will translate micro-architecture into clean, high-quality RTL and drive it through synthesis and timing closure.
Requirements
- Knowledge of AMBA and serial protocols, processors, and silicon bring-up sequences.
- Expertise in synthesis, constraints, timing closure, and equivalence checks (Formality / Conformal).
- Experience with Lint / CDC / RDC tools.
Nice to have
- Familiarity with interconnect protocols such as PCIe (Gen5/6/7) and UCIe.
- High-speed wireline / SerDes-based SoC experience
- Scripting proficiency (Python, Tcl)
Compensation
- California Pay Range
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This listing is sourced directly from Phizenix's careers page and normalized into a canonical job model.