River
Member of Technical Staff, Hardware, Compiler Engineer
Palo Alto, CA; Austin, TX · Staff+
H1B sponsorship available$200k-$420kDetected 25 days ago
C++Backend DevelopmentAlgorithmsDeep LearningPyTorchLogisticsElectrical Engineering
About the role
- You will take ownership of kernel algorithms, intermediate representations, and even modify the ISA as necessary to achieve a flexible and high performance compiler stack.
- You will be collaborating both up and down the stack with AI researchers and modelers, as well as with performance engineers and silicon architects.
Responsibilities
- Graph Lowering & Optimization: Design and implement compiler passes to lower PyTorch models into custom hardware, leveraging MLIR dialects and LLVM frameworks.
- Custom Backend Development: Develop and maintain the backend toolchain for our custom silicon, including instruction scheduling, register allocation, and hardware-specific code generation.
- Memory & Loop Transformations: Design sophisticated tiling and fusion strategies to maximize bandwidth utilization and minimize on-chip memory movement.
- Kernel Integration: Collaborate with software and hardware teams to integrate high-performance kernels (Triton/CUDA-like) into the automated compiler flow.
- Performance Profiling: Identify "compilation gaps" where the compiler fails to achieve peak hardware performance, and collaborate with the performance team for targeted optimizations to close those gaps.
- HW/SW Co-Design: Partner with the RTL and Architecture teams to change the custom ISA definitions.
- A highly collaborative mindset to push boundaries and co-design effectively with other engineers.
Requirements
- Bachelor's degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Proficiency in modern C/C++ for building robust, scalable, and high-performance compiler infrastructure.
Nice to have
- (We encourage you to apply even if you don't meet all of these)
- Hands-on experience in post-Silicon firmware and model update patches
- Experience defining and implementing custom dialects, lowering passes, and graph rewrites in an LLVM-based ecosystem.
- Knowledge of the tradeoffs between static and runtime environments, including JITs and ABIs
- Visa Sponsorship: We sponsor visas.
- We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
Skills
- Skills and Qualifications
Compensation
- Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
Benefits
- River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
- Deep hands-on experience with MLIR or XLA for deep learning workloads.
Company info
- We are scientists, engineers, and builders from the industry's top tech companies and AI labs.
- We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
- At River, our mission is to create personal AI owned and shaped by each individual.
- personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research.
Visa & Work Authorization
- We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
- We sponsor visas.
This listing is sourced directly from River's careers page and normalized into a canonical job model.