Capgemini
SoC Design Engineer
Atlanta, GA, US · Full-time
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($73,150) is below the Level I prevailing wage of $114,899. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $139,360 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Architectural and Engineering Managers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Architectural and Engineering Managers (11-9041) · Atlanta-Sandy Springs-Roswell, GA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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About the role
- Integrate complex subsystems at the SoC level, including processors, memory, and high-speed interfaces.
Responsibilities
- Collaborate with IP vendors and internal stakeholders to select and configure optimal IP solutions.
- Develop and maintain timing, power, and quality methodologies, including SDC constraints, UPF implementation, CDC/RDC analysis, and linting flows.
- Analyze power, performance, and area results and drive design optimizations to meet product objectives.
- Partner with synthesis, DFT, and physical design teams to resolve timing, power, and implementation challenges.
- Support PCB design and system integration activities to ensure successful product development and deployment
- Experience using Synopsys tool suites including VCS, Verdi, SpyGlass, Design Compiler, and RTL Architect.
- Define and document architecture specifications for SoC subsystems and contribute to overall chip architecture decisions.
- Experience developing and maintaining CDC, RDC, linting, synthesis, and power analysis flows.
- Excellent verbal and written communication skills with the ability to collaborate effectively across global engineering teams
Requirements
- Master's degree in Electrical Engineering or a related technical discipline, or equivalent industry experience.
- Four+ years of experience in SoC integration, design, or related semiconductor engineering roles.
- Proficiency with RTL design methodologies and hardware description languages including Verilog, SystemVerilog, or VHDL.
- Knowledge of MMU-based systems and cache-coherent architectures.
- Experience with RTL-to-GDS implementation flows.
- Familiarity with verification methodologies such as UVM.
- Working knowledge of embedded software development using C.
Skills
- Your Skills & Experience
- Strong experience integrating complex SoC subsystems such as processors, PCIe, DDR, or similar technologies.
- Strong scripting and automation skills using languages such as Tcl and Python.
Compensation
- $73k-$174k
Company info
- At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential.
This listing is sourced directly from Capgemini's careers page and normalized into a canonical job model.