Altera
Staff/ Senior Staff NPI Debug Engineer
San Jose, California, United States · Staff+
Sponsorship not specified$149k-$215kDetected 30 days ago
PythonData AnalysisFPGAElectrical EngineeringLeadershipCommunicationProblem Solving
About the role
- Altera is seeking a Staff / Senior Staff NPI (New Product Introduction) Debug Engineer to serve as a key senior technical leader for our most critical hardware investigations.
- You will share taskforce leadership responsibilities with other senior members of the team, acting as the primary orchestrator for investigations that heavily involve analog, mixed-signal, and power delivery challenges.
- You will analyze complex issues firsthand, define fault trees, guide parallel investigations across global engineering teams, and present root-cause findings to executive leadership.
Responsibilities
- Drive Debug Taskforces: Act as the technical lead and orchestrator for designated cross-functional "tiger teams" formed to solve critical NPI blockers, especially those involving complex analog, power, or signal integrity interactions.
- Define the Debug Strategy: Develop comprehensive fault trees, design of experiments (DOEs), and parallel investigation paths. Assign clear ownership across Design, Product, Test, Validation, and Manufacturing teams.
- Executive Communication: Lead taskforce syncs, maintain clear dashboards, and present high-level readouts, recovery schedules, and risk assessments to leadership.
- Lead complex yield analysis activities directly related to NPI investigations, including yield pareto, parametric shift analysis, tester correlation, and statistical data review.
- Identify systemic yield detractors and lead corrective actions across the foundry/fab, assembly, test, and design teams.
- Guide experimental builds and validation of engineering fixes proposed by the taskforces.
Requirements
- 6+ years of experience in hardware debug, NPI engineering, product/yield engineering, or system validation
- 6+ years leading technical taskforces to resolve critical silicon, hardware, or yield issues under tight schedules.
- 6+ years of experience driving yield analysis and yield improvement for semiconductor, FPGA, SoC, or complex hardware products.
- 6+ years of data analysis experience using Python, JMP, or equivalent
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or related technical field. Master's or PhD preferred.
Nice to have
- Master's or PhD in Electrical Engineering, Electronics, Physics, or related field.
- Strong background in analog and mixed-signal debug
- Familiarity with fault isolation (FI) and failure analysis (FA) techniques
- Exceptional technical communication skills
- capable of translating highly technical, multi-disciplinary debug data into clear risk assessments and action plans for leadership.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or related technical field.
- Master's or PhD preferred.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,000 USD
Benefits
- Influence test program development, diagnostic coverage, and outlier detection screening to prevent taskforce-level escapes.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.