Astera Labs Inc.
Regional Principal Product Application Engineer
San Jose, California, United States · Principal
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- This role will be supporting our China region.
Requirements
- Minimum of 3 years' experience in designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.
- Full professional proficiency in Mandarin (written and spoken) required to communicate directly with Asia region customer contacts
- Required Experience
- Silicon/System bring-up and debug experience in customer systems.
- Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.
- Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages.
- Experience with common data center BMC implementation, and BIOS configuration
Nice to have
- Strong academic and technical background in electrical engineering.
- At minimum, a Bachelor's in EE is required, Master's is preferred.
- Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug.
- Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred.
- Preferred experience
Compensation
- Base salary range is $185,000 to $240,000 depending on experience, level, and business need.
Company info
- Regional leads focus on development, debugging, and design-in activities related to customers in a designed geography, and help coordinate with local development teams in Astera Labs Headquarters.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.