Altera

Altera

Principal/Senior Principal Engineer - Physical Design Implementation and Signoff Methodology

San Jose, California, United States · Principal

Sponsorship not specified$232k-$341kDetected 7 days ago
PythonMachine LearningANSYSCadenceFPGAElectrical EngineeringLeadershipCommunicationCollaborationProblem SolvingMentoring

Stay score

odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level IV · 4×
Level I$124,4051 entry
Level II$155,8962 entries
Level III$187,4083 entries
Level IV$218,8994 entries

This range already reaches Level IV — the maximum four lottery entries.

DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • As an independent FPGA leader, we combine decades of silicon expertise with a startup's focus on speed and innovation.
  • This role sits on Altera's senior individual-contributor (IC) technical ladder (Senior Principal Engineer / Principal Engineer).
  • Innovation - Evaluate, qualify, and help adopt emerging EDA tools, AI/ML-based flows, and methodologies that keep Altera's implementation and signoff capability ahead of the curve.

Responsibilities

  • Implementation & signoff methodology strategy - Own the end-to-end physical design implementation and signoff methodology - including place-and-route implementation, electromigration and IR-drop (EMIR) analysis, timing signoff, and power signoff - across Altera's product portfolio.
  • Scalable, efficient closure - Architect implementation and signoff flows to scale efficiently across a growing number of concurrent designs, enabling faster and more predictable closure without linear growth in engineering effort.
  • Technology enablement - Partner with process/technology teams, EDA vendors, and design teams to qualify and deploy next-generation implementation, EMIR, timing, and power methodologies for advanced process nodes.
  • Quality and reliability - Establish golden reference flows, signoff criteria, and quality gates that protect silicon reliability and drive first-pass tapeout success.
  • Technical problem-solving - Lead root-cause analysis of complex implementation, EMIR, timing, and power signoff issues, and drive convergence across block-level and full-chip integration.
  • Cross-functional leadership - Serve as the go-to technical authority in tapeout readiness reviews, technology qualification forums, and cross-functional design reviews.
  • Mentorship - Mentor design and CAD engineers on physical design implementation and signoff best practices, raising the technical bar across the organization.
  • Implementation and signoff flows that scale efficiently to handle a growing portfolio of concurrent designs, with efficient closure and less manual firefighting as volume grows.

Requirements

  • A demonstrated track record of architecting and deploying PD implementation and signoff methodologies across multiple tapeouts and process technology nodes.
  • Hands-on proficiency with industry-standard place-and-route, EMIR, STA, and power signoff tools (e.g., Ansys RedHawk-SC, Synopsys PrimeTime/PrimePower/Fusion Compiler, Cadence Innovus/Voltus/Tempus, or equivalent).
  • Scripting and automation proficiency (Python, Tcl) sufficient to build methodology infrastructure and integrate ML pipelines directly, not only to script around flows others have built.
  • Applicants must be eligible for any required U.S. export authorizations.
  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, plus 15+ years (for Senior Principal Engineer) or 12+ years (Principal Engineer) of physical design experience, including a minimum of 8 years developing and deploying implementation or signoff methodology.
  • Deep, hands-on expertise in physical design implementation and signoff methodology, including electromigration and IR-drop (EMIR) analysis.
  • Strong command of timing signoff (STA) and power signoff flows, and the industry standards that govern them.
  • Depth expectation. Deep, demonstrate expertise in at least two of the three core domains - place-and-route implementation, EMIR analysis, and timing/power signoff - with working command of the third. Depth across all three is preferred, not required.
  • An AI/ML-driven mindset and working knowledge of applying AI/ML techniques (e.g., predictive modeling, ML-based EDA optimization, generative flow automation) to physical design implementation and signoff to significantly improve productivity and quality.
  • Solid understanding of physical design challenges at [CONFIRM
  • Excellent cross-functional collaboration and communication skills, with the ability to influence design methodology across multiple teams and sites.
  • A genuine can-do attitude - comfortable rolling up your sleeves and jumping into execution at any stage of the design cycle, from early flow architecture to late-stage tapeout firefighting.

Nice to have

  • Direct experience deploying AI/ML-based EDA solutions in production flows (e.g., ML-driven timing/power/IR prediction, automated ECO generation, anomaly detection in signoff data).
  • Experience defining methodology strategy at a Principal or Senior Principal Engineer level across multiple product generations.
  • Experience working directly with foundry PDKs and technology qualification for leading-edge process nodes.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:
  • Depth expectation.
  • Deep, demonstrate expertise in at least two of the three core domains - place-and-route implementation, EMIR analysis, and timing/power signoff - with working command of the third.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $231,500 - $341,075 USD

Benefits

  • Flow architecture - Define and continuously improve PD implementation and signoff flows and standards, ensuring accuracy, full coverage, and efficient turnaround time for every design team that depends on them.
Apply directly at Altera →Create a free account for alerts like thisView Altera immigration profile

This listing is sourced directly from Altera's careers page and normalized into a canonical job model.